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WM2619 12-bit Parallel Input Voltage Output DAC
Production Data, June 1999, Rev 1.0
FEATURES
* * * * * 12-bit voltage output DAC Single supply 2.7V to 5.5V operation DNL 0.4 LSB, INL 1.5 LSB Settling time 1s typical Low power consumption 8mW typical in slow mode - 5V supply 4.3mW typical in fast mode - 3V supply Power down mode
DESCRIPTION
The WM2619 is a 12-bit voltage output, resistor string, digital-toanalogue converter. A hardware controlled power down mode is provided that reduces power consumption to 50nW. In normal operation the device dissipates 8mW at 5V or 4.3mW at 3V. The device has been designed to interface efficiently to industry standard microprocessors and DSPs. Excellent performance is delivered with a typical DNL of 0.4 LSBs and a settling time of 1s. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage. The 12 data bits are double-buffered enabling the output to be asynchronously updated under hardware control. The device is available in a 20-pin TSSOP package. Commercial temperature (0 to 70C) and Industrial temperature (-40 to 85C) variants are supported.
*
APPLICATIONS
* * * * * * * Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation
ORDERING INFORMATION
DEVICE WM2619CDT WM2619IDT TEMP. RANGE 0 to 70C -40 to 85C PACKAGE 20-pin TSSOP 20-pin TSSOP
BLOCK DIAGRAM
VDD (11)
TYPICAL PERFORMANCE
1 VDD = 5V, VREF = 2.048V, Load = 10k/100pF 0.8
X1 DAC OUTPUT BUFFER X2 (13) OUT
REFERENCE INPUT BUFFER REFIN(12)
0.6 0.4 0.2 0 -0.2 -0.4
D[0-11] (19,20, 1-10) NWE (17) NCS (18) 12-BIT INPUT REGISTER
data
12-BIT DAC LATCH
POWER-ON RESET
POWERDOWN CONTROL
DNL - LSB
-0.6
WM2619
-0.8 -1 0 512 1024 1536 2048 DIGITAL CODE 2559 3071 3583 4095
(14) GND
(16) NLDAC
(15) NPD
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and conditions. Masterrev1.0a.doc June 17, 1999 10:52
(c)1999 Wolfson Microelectronics Ltd.
WM2619 PIN CONFIGURATION
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D1 D0 NCS NWE NLDAC NPD GND OUT REFIN VDD
Production Data
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NAME D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 VDD REFIN OUT GND NPD TYPE Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Supply Analogue input Analogue output Ground Digital input DESCRIPTION Digital data input. Digital data input. Digital data input. Digital data input. Digital data input. Digital data input. Digital data input. Digital data input Digital data input. Digital data input (MSB). Positive power supply. Voltage reference input. Analogue output. Ground. Power down. Powers down all DACs overriding their individual power down settings and all output stages. This pin is active low. Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. Write enable (active low). Chip select (active low). Parallel data input (LSB). Parallel data input.
16
NLDAC
Digital input
17 18 19 20
NWE NCS D0 D1
Digital input Digital input Digital input Digital input
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999 2
Production Data
WM2619
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device CONDITION Digital Supply voltage, VDD to GND Reference input voltage Digital input voltages Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds WM2619C WM2619I -0.3V -0.3V 0C -40C -65C MIN MAX 7V VDD + 0.3V VDD + 0.3V 70C 85C 150C 260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REFIN Load resistance Load capacitance Operating free-air temperature SYMBOL VDD VIH VIL VREF RL CL TA WM2619C 0 VDD = 2.7V to 5.5V VDD = 2.7V to 5.5V See Note 2 10 100 70 85 TEST CONDITIONS MIN 2.7 2 0.8 VDD - 1.5 TYP MAX 5.5 UNIT V V V V k pF C C
WM2619I -40 Note: Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
WOLFSON MICROELECTRONICS LTD
Production Data Rev1.0 June 1999 3
WM2619 ELECTRICAL CHARACTERISTICS
Production Data
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current IDD No load, VIH = VDD, VIL = 0V VDD = 5V, VREF = 2.048V VDD = 3V, VREF = 1.024V See Note 8 No load, all digital inputs 0V or VDD See Note 9 DAC code 128 to 4095, 10%-90% See Note 10 DAC code 128 to 4095 See Note 11 Code 2047 to 2048 SNR fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25C See Note 12 fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25C See Note 12 fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25C See Note 12 fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25C See Note 12 65 1.6 1.4 0.01 3.0 2.7 10 mA mA A 2k to 10k load See Note 7 0 0.1 VDD - 0.4 0.3 V % INL DNL ZCE GE d.c. PSRR See Note 1 See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 12 bits SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
1.5 0.4
3 0.25 0.5 3 1
4 1 20 0.5
LSB LSB mV % FSR mV/V ppm/C ppm/C
Power down supply current
Dynamic DAC Specifications Slew rate 8 V/s
Settling time
1
s
Glitch energy Signal to noise ratio
5 78
nV-s dB
Signal to noise and distortion ratio
SNRD
58
67
dB
Total harmonic distortion
THD
-68
-60
dB
Spurious free dynamic range
SPFDR
60
72
dB
Reference Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREFIN CREFIN VREF = 1VPP at 1kHz + 1.024Vdc, DAC code 0 VREF = 0.2VPP + 1.024V d.c. DAC code 2048 10 5 -60 1.4 M pF dB MHz
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999 4
Production Data
WM2619
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER Digital Inputs High level input current Low level input current Input capacitance Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs. IIH IIL CI Input voltage = VDD Input voltage = 0V 8 1 -1 A A pF SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
WOLFSON MICROELECTRONICS LTD
Production Data Rev1.0 June 1999 5
WM2619 SERIAL INTERFACE
tSUDWE D [0:11] X tSUCSWE NCS tWWE NWE tSUWELD NLDAC tWLD Data tHD X
Production Data
Figure 1 Timing Diagram Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) SYMBOL tSUCSWE tSUDWE THD tSUWELD tWWE tWLD TEST CONDITIONS Setup time NCS low before positive NWE edge Setup time data ready before positive NWE edge Data hold after positive NWE edge Setup time NWE high before NLDAC low High pulse width of NWE Low pulse width of NLDAC MIN 13 9 0 0 10 10 TYP MAX UNIT ns ns ns ns ns ns
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999 6
Production Data
WM2619
TYPICAL PERFORMANCE GRAPHS
3 VDD = 5V, VREF = 2.048V, Load = 10k/100pF 2
1
INL - LSB
0
-1
-2
-3 0 512 1024 1536 2048 DIGITAL CODE 2559 3071 3583 4095
Figure 2 Integral Non-Linearity
3
5
VDD = 3V, VREF = 1V, Input Code = 0
4.5 2.5 4
VDD = 5V, VREF = 2V, Input Code = 0
3.5 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 0 1 2 3 4 5 ISINK - mA 6 7 8 9 10 2
3
1.5
2.5
2
1 1.5
1 0.5 0.5
0
0 0 1 2 3 4 5 ISINK - mA 6 7 8 9 10
Figure 3 Sink Current VDD = 3V
Figure 4 Sink Current VDD = 5V
2.065
4.105
VDD = 3V, VREF = 1V, Input Code = 4095
2.06 4.1
VDD = 5V, VREF = 2V, Input Code = 4095
2.055
4.095
OUTPUT VOLTAGE - V
2.05
OUTPUT VOLTAGE - V 0 1 2 3 4 5 ISOURCE - mA 6 7 8 9 10
4.09
2.045
4.085
2.04
4.08
2.035
4.075
2.03
4.07
2.025
4.065 0 2 4 ISOURCE - mA 6 8 10
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD
Production Data Rev1.0 June 1999 7
WM2619 DEVICE DESCRIPTION
GENERAL FUNCTION
Production Data
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 2(VREF ) INPUT 1111 1111 : 0000 0000 1111 : 0000 0000 1111 CODE 4096 OUTPUT 2(VREF ) : 0001 0000 1111 2(VREF ) 2(VREF ) 2049 4096 4095 4096
1000 1000 0111
2048 = VREF 4096 2047 4096 1 4096
2(VREF ) :
0000 0000
0001 0000
2(VREF )
0V
Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10M and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
The WM2619 has two configuration options that are controlled by device pins.
DEVICE POWERDOWN
The device can be powered-down by pulling pin NPD (pin 15) high. This powers down the DAC. This will reduce power consumption significantly. When the power down function is released the device reverts to the DAC code set prior to power down.
DAC UPDATE
The NLDAC pin (Pin 16) can be held high to prevent serial word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch.
PARALLEL INTERFACE
The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS (Pin 18) low.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999 8
Production Data
WM2619
PACKAGE DIMENSIONS
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm ) DM008.C
b
20
e
11
E1
E
GAUGE PLANE 1 10
D 0.25 c A A2 A1 L
-C0.05 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 6.40
4.30 0.45 o 0
Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153
MAX 1.20 0.15 1.05 0.30 0.20 6.60
4.50 0.75 o 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
Production Data Rev1.0 June 1999 9

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